Pulse modulator

ABSTRACT

A low level input pulse signal from T 2  L logic is delivered to the  it of a ground deck driver which is transformer-coupled to a floating deck driver. The leading edge of the input pulse serves to enable or trigger a first FET driver, which is coupled to the gates of a plurality of series-connected FETs via a first transmission line transformer. The triggering of the FET driver serves to turn-on the series-connected FETs so that the same delivers a high voltage signal to an output load. A second FET driver is coupled to the gates of another plurality of series-connected FETs, which serve as a &#34;tail-biter&#34; to terminate the power to the output load. And, a third FET driver is coupled to the gates of the first-mentioned series-connected FETs to turn the same to the OFF state. The second and third FET drivers are coupled to their respective series-connected FETs via respective transmission line transformers. The trailing edge of the input trigger pulse enables the second and third FET drivers to concurrently turn-on the tail-biter FETs and turn-off the first-mentioned, series-connected FETs.

STATEMENT OF GOVERNMENT RIGHTS

The Government has rights in this invention pursuant to Contract No.DAAK20-83-C-0390 ordered by the Department of the Army.

TECHNICAL FIELD

The present invention relates to a high voltage nanosecond pulsemodulator which employes field effect transistros.

BACKGROUND OF THE INVENTION

The patent to W. E. Milberger (a co-inventor of the present invention)U.S. Pat No. 4,425,518, issued Jan. 10, 1984, discloses field effecttransistor (FET) pulse apparatus which provides high voltage pulse ofshort duration. The pulse apparatus of the patent is capable ofproviding pulse voltages of several kilovolts with pulse widths ofapproximately 20 nanoseconds (nsec). The patented pulse modulator wasdesigned for use with the transmitter of ECM systems, for example.

The transmitters of advanced MMW (millimeter wave) radar systems requirehigher voltage pulses, of shorter duration, than the pulse modulator ofthe patent can deliver. The same is true for the pulses required totrigger the Pockels cell of advanced, high power, laser transmitters.Moreover, these more advanced systems require (modulation) pulses whichhave a very fast "fall-time" that is at least equal to the turn on or"rise-time". The pulses produced by the pulse apparatus of the citedpatent have a relatively slow fall-time; i.e., the fall-time isconsiderably slower than the rise-time.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to provide a pulsemodulator that produces pulses of very high voltage, yet of extremelyshort duration.

A related object of the invention is to provide pulses which have a veryfast fall-time substantially equal to their rise-time.

These and other objects are attained in accordance with the presentinvention wherein a conventional trigger pulse is utilized to initiatethe high voltage nanosecond pulse generation operation. The triggerpulse is coupled to a plurality of FET drivers via grounddeck-to-floating deck transformer coupling. A first FET driver iscoupled to the gates of a plurality of series-connected FETs via a firsttransmission line, power splitting, transformer. The leading edge of thetrigger pulse enables the first FET driver to turn the series-connectedFETs to an "ON" state and thereby deliver a high voltage signal to anoutput load (e.g., the control element of a MMW transmitter tube). Asecond FET driver is coupled to the gates of another plurality ofseries-connected FETs, which serve as a "tail biter" to terminateabruptly the power to the output load. And, a third FET driver iscoupled to the gates of the first-mentioned series-connected FETs toturn the same to the "off" state. The second and third FET drivers arecoupled to their respective series-connected FETs via respectivetransmission line, power splitting, transformers. The trailing edge ofthe input trigger pulse enables the second and third FET drivers toconcurrently turn-on the tail-biter FETs and turn-off thefirst-mentioned, series-connected FETs.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more fully appreciated from the following detaileddescription when the same is considered in connection with theaccompanying drawings, in which:

FIG. 1 is a schematic circuit diagram of a high voltage, nanosecond,pulse modulator in accordance with the present invention; and

FIG. 2 illustrates a transmission line, power splitting, transformerutilized in accordance with the invention.

DETAILED DESCRIPTION

The pulse modulator circuit of the. present invention will first bebriefly described in functional terms to provide a general understandingof the operation thereof. This will be followed by a detailedexplanation of the various design features of the invention which haveproved to be particularly advantageous in the production of the desiredhigh voltage (up to 20 kilovolts), short duration (e.g. 10 nsec.)pulses. The pulse modulator, in fact, is capable of producing pulsesranging in width from 10 nsec to 1.0 sec. or more (even up to d-c).

The FIG. 1 shows the modulator used as a floating deck pulser. Theground deck references are designated as and the floating deckreferences (e.g., transmitter tube cathode potential) are designated as. The floating deck portion of the pulser is controlled from on-offtrigger pulse commands derived from the ground deck. These on-offtrigger pulse inputs are generated by T² L logic, for example, and areapplied to the input of the DS-0026 two-phase ground deck driver 11. Asin the cited patent, the input trigger pulses are of limited pulseamplitude (e.g. 5-20 volts). When terminals 2 and 4 of driver 11 aretied together, a floating deck ON trigger, corresponding to the leadingedge of the T² L input pulse, will appear at terminal 2 of the floatingdeck driver 12. This is accomplished by the coupling transformer 13which provides both pulse differentiation and high voltage isolation.The 0026 drivers 11 and 12 are power amplifiers, which are commerciallyavailable from National Semiconductor Inc., for example. The floatingdeck driver 12 provides triggers to the pair of 2N6660 FET drivers 14and 15. The trigger to the gate of FET driver 14 corresponds to theleading edge of the T² L input pulse, and the trigger to the gate of FETdriver 15 corresponds to the trailing edge of the same. The drivers 14and 15, in turn, supply gate drive to the on-off IRF832 transmissionline drivers 16, 17 and 18, via the transformers 31 and 32.

Each of the three FET drivers 16-18 provides a 400 volt trigger signalto twelve ferrite toroid cores which charges or discharges the inputgate capacitance(s) of a respective series-connected FET chain, as willnow be described.

The FET driver 16 is enabled or turned on prior to the enabling of theFET drivers 17 and 18. This is illustrated in FIG. 1 wherein the triggerinput to the gate of FET 16 precedes the trigger applied to the gates ofFETs 17 and 18 by an amount or duration D, which is typically equal tothe pulse width of the T² L input pulse. Prior to a gate trigger input,the drains of FETs 16-18 are essentially at the +400 volts. The sourceleads of FETs 16-18 are connected to floating deck ground and,therefore, when the FETs are triggered or turned on the drain leads ofthese FETs drop precipitously in voltage and a negative 400 volt triggersignal is developed and delivered to the transformer cores connectedthereto.

Three transmission line transformers 31-33 are utilized in accordancewith the invention, each of which comprises a plurality of primary andsecondary windings (e.g., effectively twelve primaries and, of course,twelve secondaries each). These unique transmission line transformerswill be described in detail hereinafter. The primaries of transformers31-33 are respectively connected to the drain leads of the FET drivers16-18. The gates of the series-connected FETs 41 (twelve in number) arerespectively connected to the twelve secondaries of transmission linetransformer 31 via the diodes 42. As indicated by the conventional useof dots on the primary and secondary windings of transformer 31, thenegative trigger in the primaries is inverted to a positive trigger inthe secondaries and the same is coupled to the gates of the FETs 41.Thus, the series-connected FETs 41 are turned on simultaneously andserve to deliver a high voltage signal to the output 30 via the smallresistance (47 ohms) 35. The series-connected FETs therefore function asan "ON switch".

The primaries of transmission line transformer 32 are connected to thedrain lead of FET 17. When the FET 17 is turned on, at a timecorresponding to the trailing edge of the input T² L pulse, a negativetrigger is generated in the primary windings of transformer 32 and thistranslates to a negative trigger in the secondaries of transformer 32,as suggested by the dots in the primaries and secondaries of the lattertransformer. As will be apparent to those in the art, this isaccomplished by a simple reverse connection to these secondaries. Thenegative trigger in the secondaries of transformer 32 is coupled to thegates of the series-connected FETs 41 via the zener diodes 44. As willbe explained in greater detail hereinafter, the negative trigger servesto abruptly turn-off the FETs 41.

The primaries of transmission line transformer 33 are connected to thedrain lead of FET 18. Since the FETs 17 and 18 are enabled concurrently,a negative trigger occurs in the primaries of transformer 33simultaneously with the negative trigger in the primaries of transformer32. This results in a positive trigger in the secondaries (twelve) oftransformer 33, which is coupled to the gates of the series-connectedFETs 45 via the diodes 46. Thus, the (twelve) series-connected FETs 45are turned on in unison and this serves to terminate the high voltageoutput signal at output 30. And, more importantly, the FETs 45 whichcomprise a "Tail Biter" switch are turned on substantially concurrentlywith the turn off of the FETs 41 which comprise the "On Switch".

As previously indicated, the ground deck driver 11 accepts low levelinput signals from T² L logic, for example, and the same istransformer-coupled to the floating deck driver 12. Five inches ofcreepage distances is used to isolate the two decks. However, if onlylimited pulse widths are required (25-400 nsec), the pulser may beoperated on the ground deck using a coupling capacitor.

The 0026 ground deck pulser 11 can be connected to either lengthen orshorten the T² L input pulse width. To shorten the pulse, the length ofline (e.g., coaxial) between the terminals 2 and 4 is increased; i.e.,the line provides added delay and the leading edge trigger at terminal 2is thus closer in time to the trailing edge trigger at terminal 4 tothereby effectively shorten the appearance of the input pulse width.Conversely, to lengthen the pulse the T² L input is applied to terminal2 with the extended line between the two input terminals. For pulsewidths in excess of 5 microseconds, terminals 2 and 4 are separated. ONtriggers are then supplied to terminal 2 at about the 200 kHz rate. Thissustains the modulator output pulse as long as desired. The pulse lengthcan be terminated by ceasing the input to terminal 2 and then applying asingle OFF trigger to terminal 4.

Both the "ON Switch" and "Tail Biter" transistor chains use diode gateinput circuits to charge the gate input capacitance of the FETs. Anegative OFF trigger is used to discharge the FET input capacitance forreset. This is done by applying a -20 volt pulse to the anode of the 12volt (IN759A) zener which is coupled to the FET 41 gates. Since the FETgate is charged up to +12 volts prior to the application of the OFFtrigger, the negative -20 volt pulse provides a rapid discharge forreset. This insures that the ON Switch is hard off when the Tail Biterswitch is triggered. To reduce the capacitance which the ON Switch sees,back-bias diodes 51 (6-SENR 273s) are used to isolate capacitance of theTail Biter from the ON Switch. The back-bias recharge tine isapproximately 10 microseconds after the Tail Biter is triggered Thistime constant also establishes the maximum pulse repetition frequency(e.g., PRF=50 kHz) at which the pulser may be operated without TailBiter capacitance loading.

The 47-ohm series output resistance 35 provides load damping and currentlimiting for tube arcing conditions. Positive going transient currentsthat flow as a result of tube arcing are diverted to the floating deckvia the internal diodes that shunt each ON chain transistor. Conversely,negative going currents are diverted to the -33,200 v. supply throughthe SENR 273 diodes 52 that juncture at the pulser output. It may benecessary to shunt the 3200 volt pulser supply with a zener or spark gapto limit the level to which the pulser storage capacitance chargesduring negative going transients.

An advantageous design feature is the inclusion of a shunt discretecapacitance (560 pf) from the gate to source of all ON and OFF switchFETs. This capacitance suppresses parasitic oscillations and preventsthe FETs from turning back on via the Miller integration capacitancewhen the device is programmed to turn off.

Another advantageous design feature is the inclusion of the 5.1 ohmresistance placed in series with each gate input diode 42. Theresistance limits the reverse recovery current through the diode whenthe gate command is initiated. As a result of this feature, pulse "afterbirth" (false turn on after the off command is completed) is prevented.

The transmission line transformers 31-33 are constructed in the mannershown in FIG. 2 of the drawings. A copper wire 21 is centrally disposedinside a cylindrical tube 22 of glass or quartz, for example, ofapproximately one-quarter inch diameter. The wire 21 serves as theprimary winding. Twelve toroid cores 23 are spaced, equidistantly, alonga length of the tube. The toroid cores are, of course, the secondariesand each is connected to one of twelve series-connected FETs. Thistransmission line, power splitting, transformer configuration provides anumber of particularly advantageous features, namely: equal powersplitting with a very high cut-off frequency; voltage isolation betweenadjacent cores; inner to outer conductor voltage isolation greater than100 kilovolts (limited only by creepage distance, if glass dielectricrods are used); and, extremely low primary to secondary capacitance from1 to 4 pf. (this extends the cut-off frequency of the line and permitsseries operation of FET transistors).

The pulse modulator of the present invention was developed primarily forthe purpose of modulating the control element (modulation anode,aperture grid, shadow grid or intercept grid) of millimeter wavetransmitter tubes. However, since the present modulator is capable ofproviding pulse voltages up to 20 kilovolts it can be readily utilizedwith other and different apparatus using control elements, includingcathode and deflection plates. Such apparatus include many categories ofr-f. vacuum tubes and CRTs. Furthermore, the fast turn-on response ofthe instant device can greatly improve the overall transport delay ofECM transponders. For faster pulse rise and fall times, the circuit maybe configured as an MHP (multichip hybrid package) to minimize therestricting circuit inductance. In the spirit of the invention, thepulse modulator can also be used as a pulse width regulator and d-c tod-c chopper converter, as similarly noted in the cited patent.

The FET transistor types indicated in FIG. 1 of the drawings arecommerically available devices and, moreover, are only given by way ofexample. As will be obvious to those in the art, other known transistortypes may be readily substituted for those indicated in FIG. 1. Forexample, for the IRF832 FETs one could readily substitute TP4N50 FETdevices, which are also commercially available. The above is also truefor the diode types indicated in FIG. 1. The indicated values for theresistances, capacitances, and bias supplies are intended to be merelyexemplary and the modulator of the invention is in no way limitedthereto. For a 20 kilovolt output, for example, substantially largerbias supplies would be necessary. Without further belaboring the point,it should be obvious at this time that the above-described arrangementis merely illustrative of the application and of the principles of thepresent invention and numerous modifications thereof may be devised bythose skilled in the art without departing from the spirit and scope ofthe invention.

What is claimed is:
 1. Apparatus for generating a high voltage, shortduration, pulse signal in response to a low level input pulse signalcomprising a ground deck driver means transformer-coupled to a floatingdeck driver means, means for delivering said input pulse to said grounddeck drive means, said floating deck driver means serving to generate afirst trigger pulse which corresponds to the leading edge of said inputpulse and a second trigger pulse which corresponds to the trailing edgeof the same, a first FET driver means coupled to the gates of aplurality of series-connected FETs and responsive to said first triggerpulse to enable said series-connected FETs to deliver a high voltagesignal to an output load, a second FET driver means coupled to the gatesof a second plurality of series-connected FETs and responsive to saidsecond trigger pulse to enable said second plurality of FETs toterminate said high voltage signal, and a third FET driver means alsocoupled to the gates of the first-mentioned series-connected FETs andresponsive to said second trigger pulse to disable said first-mentionedseries-connected FETs.
 2. Apparatus as defined in claim 1 wherein saidfirst-mentioned series-connected FETs are disabled substantiallyconcurrently with the enabling of said second plurality of FETs. 3.Apparatus as defined in claim 2 including three transmission line powersplitting transformers, each of which serves to couple a respective oneof said FET driver means to said series-connected FETs.
 4. Apparatus asdefined in claim 3 wherein said transmission line transformers eachcomprise a conductive wire mounted in a cylindrical glass tube, and aplurality of toroid cores spaced equidistantly along a length of saidtube.
 5. Apparatus as defined in claim 4 wherein said conductive wirecomprises a primary winding and said plurality of toroid cores comprisesecondary windings of a transformer, said cores being equal in number tothe number of series-connected FETs.
 6. Apparatus as defined in claim 2including a shunt discrete capacitance connected from the gate to sourceof each FET in said series-connected FETs.
 7. Apparatus as defined inclaim 6 including resistance means series connected with said outputload for providing predetermined load damping and current limiting. 8.Apparatus as defined in claim 7 including means for preventing a falseturn-on of the FETs of the first-mentioned series-connected FETs afterthe same have been disabled.